SPIHT implemented in a XC4000 device

In this paper we present an efficient FPGA implementation of the ’Set Partitioning in Hierarchical Trees’ (SPIHT) algorithm of Said and Pearlman [1] in combination with an arithmetic coder. The FPGA implementation is applied within a partitioned approach for wavelet-based lossy image compression [2]. The basic SPIHT algorithm uses dynamic data structures that make a hardware realization difficult. We illustrate in detail how these dynamic data structures can be implemented in the FPGA without the use of external memory. We present a hardware realization which can be run with a frequency of 40 MHz in a Xilinx XC4000 device. The design requires 23% less internal memory as the recently published algorithm ’SPIHT Image Compression without Lists’ of Wheeler and Pearlman [5].